Semiconductor metrology is an important aspect in improving yield, reducing manufacturing costs, and shortening the product development cycle through its ability to monitor and detect defects at each stage of semiconductor processing. As features sizes become smaller and the materials used in semiconductor processing change, metrology solutions must also be able to accommodate these changes.
For example, low-k (k<3.9) and ultralow-k (ULK) (k<2.3) dielectrics have been introduced to reduce parasitic capacitance between metal interconnect layers. Unfortunately, ULK dielectrics have exhibited a sensitivity to etching and ashing processes, which can cause defects and decrease electrical reliability.
Once such dielectric is organo-silicate glass (OSG). To further decrease the dielectric constant (k) of OSG, the porosity of OSG may be varied through the replacement of Si—O with Si—C bonds by plasma-enhanced chemical vapor deposition (PECVD) to form carbon doped oxide (CDO). However, the increased carbon content from the carbon doping process can reduce the OSG's robustness and can increase the collateral plasma induced damage during reactive ion etch (RIE) photoresist stripping. In particular, oxygen plasmas will preferentially attack weaker Si—C bonds in ULK OSG and thus strip carbon, cause densification, and result in increased k values. In addition, carbon stripping by plasma processes makes low-k and ULK interlayer dielectrics (ILD) more prone to water damage during subsequent wet cleaning processes.
FIG. 1 illustrates polymer residue and damage to a ULK dielectric 101 after both an etching and post-etch cleaning process. As shown in FIG. 1, a mask layer 102 protects a top surface of the ULK dielectric 101 during the etching process to expose a lower Cu interconnect 103. However, as illustrated in FIG. 1, polymer residues may remain on sidewalls of the trench and/or via etched into the ULK dielectric, and the ULK dielectric 101 may have damage.
Consequently, the successful patterning of next-generation ULK/Cu interconnects through various non-damaging etching, ashing, and cleaning processes represents an increasingly challenging task to the semiconductor industry.
In addition to the challenge of handling weak porous ULK materials, a lack of sensitive (e.g., nanoscale level) metrology to guide systematic development of plasma etching, restoration, and cleaning processes has been an issue for semiconductor fabrication processes as feature sizes continue to shrink. Accordingly, there continues to be a need in the art for metrology with sub-10 nm sensitivity to guide next generation semiconductor process development and integration efforts.